Minimizing device variation continues to grow in importance as a device is scaled from node to node. However, total variation is increasing for many device components as the device is scaled and so finding ways to reduce these affects is critical to delivering product level importance. For example, one element that is introducing additional variation is across chip spacer thickness variation.
More specifically, as silicon technologies offer constantly increasing levels of integration and scaling, integrated circuit designers are continually challenged to increase productivity and produce larger and larger designs with the same or less resources. Smaller circuit elements, sometimes referred to as “macros,” each of which include a predetermined structure for a part of an integrated circuit (IC) can be used repetitively for addressing this challenge. For example, the use of repetitive circuit elements eliminates the need for the IC designer to continually re-design sections of the chip, and therefore improves productivity. As a result, design reuse methodology involving the use of IC circuit elements has become an essential part of IC design.
However, the designer that uses IC circuit elements is challenged to provide a product that has predictable functioning for these IC circuit elements. One challenge is matching the electrical behavior of two or more instances of the same circuit element in different locations in an IC design. This is generally at odds with automatically generated dummy shapes, which are placed in the overall design after the layout is complete, and after the designer has performed all circuit analyses.
In particular, if the design system uses automatically placed “dummy fill,” or other auto-generated dummy shapes, the dummy fill shapes will be automatically placed around the circuit element. If the circuit element is a sensitive circuit, the designer may wish to insure that every instance of the circuit element function matches as identically as possible to every other instance within the IC. This is at odds with auto-generated dummy shapes, as they are typically located on a consistent grid across an IC design such that different instances of the circuit element may find themselves in substantially different local environments. That is, there is no guarantee that different instances of the same circuit element will see the same local environment, e.g., dummy fill and hole shapes, when placed within the IC design.
Any resulting mismatch in electrical parameters (e.g., resistance, capacitance, etc.) is unknown to the designer, and acts to degrade the function of the precision circuits in question. More specifically, even though the transistors may be designed the same, the resultant device is a non-uniform design due to the placement and shape of the dummy fill shapes. That is, the shape and density of the transistors (gates) of the device will affect the area in which dummy fill shapes can be placed on the chip which, in turn, will affect the characteristics of the transistor.
As an example, the density of the device will affect the shape and number of the dummy fill shapes, i.e., the more transistors the less space for dummy fill spacers. And, due to such variations, the transistor performance and characteristics will be affected which results in a tradeoff between speed and power consumption. For example, non-uniformity in design results in transistors of faster and slower speeds, as well as transistors that consume more and less power. Taking this as a starting point, the device will be limited, e.g., only as fast, by the slowest of the transistors. Likewise, the device will consume more power.
In order to address this issue, many designers attempt to inhibit the automatic generation of dummy shapes in the vicinity of sensitive circuits, and place all required dummy shapes by hand. This approach, however, is more difficult for the designer, and is generally detrimental to the overall manufacturability and process window. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.